In most modern computer systems, the input or output device is typically controlled by a central processing unit through an input/output controller. For instance, FIG. 1 shows how an output device, such as a monitor 5, is controlled by a central processing unit (CPU) 1.
In FIG. 1, video controller 2 and screen random access memory (RAM) 3 are coupled to the CPU 1 through address, data and control buses 6. The CPU sends to the screen RAM 3 data to be displayed The screen RAM 3 receives the address and data signals from the CPU 1 so that the CPU 1 can change the screen image as expected. The CPU sends control signals and some basic display parameter data signals to the video controller 2 to control the display of the monitor 5. The video controller 2 operates in accordance with the commands of the CPU 1 and, through the address, control and data buses 10, causes the data signal 8 of the screen RAM 3 to be transmitted to processing logic 4. The processing logic 4 is controlled by the control signal 7, such as horizontal synchronize and vertical synchronize signals, from the video controller 2. The monitor 5 receives the data signals 9 from the processing logic 4 and displays the data as a result of the control signal 7. Furthermore, if the screen RAM 3 is a dynamic random access memory (DRAM), the video controller 2 also refreshes the DRAM through the buses 10 to keep intact the stored data in the screen RAM 3.
The video controller 2 includes at least a plurality of registers that must be initialized by the CPU 1. The CPU 1 communicates with the registers through the data bus. These registers hold basic system parameters such as the number of horizontal lines for each character row, number of lines per field, the cursor location, and whether interlaced or non interlaced scan is desired, etc. These default values of the parameters are written into the registers of the video controller 2 by the CPU 1 after the completion of the reset step of the system. If the user of the system desires a display mode different from that of the default values, he may input the desired values of the parameter into the registers to change the display mode. These parameters control the operation of the video controller 2, thus making it produce the desired screen display on the monitor 5. More detailed descriptions of the video controller may be found in the book of Gerry Kane, CRT Controller Handbook, Osborne/McGraw-Hill, Berkeley, Calif, 1980.
For some other input/output controllers which have several modes of operation, the particular mode in use at any time is also determined at least by the bits in a command or status register which is included in the input/output controller. The command register is written to by the CPU, so that the CPU can command the input/output controller to operate in a given mode, and the CPU can change these commands as the program progresses. The status register is written into by an external device. It contains the information about the status of the external device such as if the printer is out of paper, if the tape drive needs another character, and so on. The CPU can read the status register to monitor the progress of data transfers and take appropriate action when required. A complete discussion on the peripheral interface controller can be found in the book, "Using Microprocessors and Microcomputers: The 6800 Family" by Greenfield and Wray, Wiley, N.Y., 1981.
In general, the above described input/output registers of the input/output controller are first reset after the power-on of the system. In most cases, the CPU generates a RESET signal to each bit of the registers while resetting. The input/output controller needs this reset step to function as expected. Afterwards, the CPU writes the default value into the input/output register to begin a default mode of operation of the input/output device. The input/output register may contain 1 bit or more of bits, depending on the requirement and complexity of the system.
In general, the input/output register is made of flip-flops and each bit of the register contains one flip-flop. In conventional design, the D type flip-flop (D-FF) with reset shown in FIG. 2 is implemented in the registers of the input/output controller. The operation of a D-FF with reset may be found in any digital design literature. The timing of the signals in FIG. 2 may be found in FIG. 4. In FIG. 2, the Clock (C) pin is connected to the system write signal XWJ which in our example is an active low signal. The D pin is connected to the system DATA signal. The reset pin is connected to the RESET signal which is generated from the electronic data processing system. In our example the system reset signal RESET is active low. The QQ output is low during the time RESET signal is low for reset purpose and remains low afterwards until the positive-going edge of the system write XWJ signal, at which time the data is strobed in and then latched by the D-FF.
In the prior art, each different input/output device, in general, has its own input/output controller in form of an integrated circuit(IC). However, it has been a recent trend that all input/output controller circuits are integrated on a single integrated circuit to miniaturize the data processing system. This is sometimes called the super input/output controller system. Since all input/output controller systems have been integrated on a single integrated circuit, it is not surprising that there may be several hundred of the above mentioned input/output registers. This results, on the average, in several thousand D-FF's with reset on a single integrated circuit. Therefore, a substantial amount of cell area is occupied by the input/output registers.
It is therefore one objective of the instant invention to reduce the chip cell area occupied by the input/output registers by providing a control circuit together with the implementation of a D-latch instead of the conventional D-FF with reset.